1. Field of the Invention
This invention relates to paging systems and, more particularly, to a paging system for translating virtual addresses having more than 32 bits.
2. Description of the Related Art
The x86 architecture (also known as the IA-32 architecture) has enjoyed widespread acceptance and success in the marketplace. Accordingly, it is advantageous to design processors according to the x86 architecture. Since such processors may execute software from the large body of software written for the x86 architecture, computer systems employing these processors may enjoy increased acceptance in the market due to the large amount of available software.
As computer systems have continued to evolve, 64-bit address size (and sometimes operand size) has become desirable. A larger address size allows for programs having a larger memory footprint (the amount of memory occupied by the instructions in the program and the data operated upon by the program) to operate within the memory space. A larger operand size allows for operating upon larger operands, or for more precision in operands. More powerful applications and/or operating systems may be possible using 64-bit address and/or operand sizes. Thus, it may be desirable to provide an architecture which is compatible with the x86 processor architecture but which includes support for 64-bit processing as well.
Unfortunately, extending the x86 processor architecture to 64 bits may be problematic. For example, extending virtual addresses to 64 bits may present challenges. Virtual addresses allow a processor to map pages of virtual memory space to pages in actual physical memory space and/or disk storage space. Before the actual physical memory space can be accessed, the virtual addresses need to be translated to physical addresses. This process is known as address translation or memory mapping, and may be performed by hardware, software, or a combination of both. Typically, virtual addresses are translated to physical addresses using some sort of paging system. These paging systems may be constructed in a way that depends upon the expected virtual and/or physical address sizes. Thus, if virtual addresses are to be extended to 64 bits, the paging system may need to be redefined, creating additional compatibility issues.
Currently, several paging systems are available for the x86 architecture. One such paging system is shown in FIG. 1. In this paging system, a 32-bit virtual address 101 is being translated to a physical address 121. Several paging tables 110, which are used to translate the virtual address, and a 4 kilobyte (Kb) page of physical memory 120 are also shown. Each of the paging tables may be contained in a 4 Kb page that can contain up to 1024 (210) 32-bit entries. In this system, the page directory base register, CR3, points to the base address of first paging table, the page directory table 110a. The page directory table entries each contain a pointer, and each pointer is a base address of a page table such as page table 110b. The upper 10 bits 31:22 of the virtual address 101 specify an offset within the page directory 110a. Thus, bits 31:22 and the pointer in CR3 can be used to locate entry 111a in the page directory table 110a. 
In the illustrated example, the page directory entry 111a contains a pointer to the base address of page table 110b. The middle field of the virtual address 101, bits 21:12, specifies an offset within page table 110b. This offset and the pointer in page directory entry 111a can be used to locate page table entry 111b. The page table entry 111b contains a pointer, which is a base address of a page of physical memory 120. The offset specified in the lowest 12 bits 11:0 of the virtual address 101 is an offset within the page of physical memory. Thus, the base address found in the page table entry 111b can be concatenated with the offset specified in bits 11:0 of the virtual address to get the physical address 121.
One variation of the paging system shown in FIG. 1 may simply use one paging table. CR3 may point to a base address of a page directory table, and the upper bits 31:22 of the virtual address may specify an offset within that page directory table. The entry in the page directory table located using that offset may contain the base address of a page of physical memory. The lower bits 21:0 of the virtual address may then specify the offset within that page to specify the physical address. Because 22 bits are used to specify the offset, the pages of physical memory can be 4 Megabytes (Mb) in size.
In FIG. 2A, three paging tables 110a-110c (collectively, paging tables 110) are used for memory mapping. The page directory base register 34, CR3, points to a base address of a page directory pointer table 210c. The highest order pair of bits 31:30 provides an offset within page directory pointer table 210c. Since two bits are used for the offset within the page directory pointer table 210c, as opposed to the nine bits used for the other paging tables 210a and 210b, the first paging table is smaller than the other two paging tables. Thus, page directory pointer table 210c may contain a maximum of four entries, while the other two paging tables 210a and 210b may contain up to 512 (29) entries.
In FIG. 2A, three paging tables 110 are used for memory mapping. The page directory base register 34, CR3, points to a base address of a page directory pointer table 210c. The highest order pair of bits 31:30 provides an offset within page directory pointer table 210c. Since two bits are used for the offset within the page directory pointer table 210, as opposed to the nine bits used for the other paging tables 210a and 210b, the first paging table is smaller than the other two paging tables. Thus, page directory pointer table 210c may contain a maximum of four entries, while the other two paging tables 210a and 210b may contain up to 512 (29) entries.
The paging tables 210a-210c (collectively, paging tables 210) in FIG. 2A may be used to translate a virtual address 201 to a physical address in a manner similar to that described with respect to FIG. 1. For example, the page directory pointer table entry 211c contains the base address of a page directory table 210a. Likewise, the directory bits 29:21 in the virtual address 201 identify an offset within the page directory table 210a, and the entry 211a located using that offset contains a pointer to a page table 210b. The pointer to the page table and the table bits 20:12 in the virtual address 201, which describe an offset within the page table 210b, can be used to locate a page table entry 211b. This page table entry 211b contains a base address of a page 220 in physical memory, and this base address can be concatenated with the offset bits 11:0 in the virtual address 201 to generate the physical address 221.
FIG. 2B shows a similar x86 paging system for 36-bit physical addresses. Unlike the system shown in FIG. 2A, this system maps virtual addresses to 2 Mb pages and uses two paging tables. Because the physical pages are 2 Mb in size, as opposed to 4 Kb, more bits of the virtual address may be used to specify the offset. Thus, in this embodiment, the lowermost 21 bits of the virtual address specify an offset within a physical page of memory, allowing each page to be 221=2 Mb in size. Generally, the paging tables shown in FIG. 2B may be used in much the same manner as those shown in FIG. 2A.
All of the above paging systems are limited to 32-bit virtual addresses. If more than 32 bits are used, the above systems will not be able to provide unique mapping of virtual addresses to physical address. Therefore, these address translation systems would be unworkable with larger virtual addresses.
Various embodiments of methods and systems for mapping virtual addresses having more than 32 bits to physical addresses are disclosed. Generally, these embodiments may provide unique mappings of virtual addresses having more than 32 bits to physical addresses by using all of the implemented virtual address bits when traversing a series of paging tables. For example, instead of using two or three paging tables to map virtual addresses, one embodiment may use four paging tables. Thus, if 9 virtual address bits are used to specify each offset within each level of paging tables and 12 virtual address bits are used to specify an offset within a physical page, such an embodiment provides unique mappings of 4*9+12=48-bit virtual addresses. Certain embodiments may also provide backward compatibility with 32-bit applications.
In one embodiment, a processor may include an execution core configured to generate a virtual address and a translation unit configured to translate the virtual address to a physical address by accessing multiple paging tables. For example, the translation unit may be configured to access a first paging table entry using a first base address of a first paging table and a first offset comprised within a first portion of the virtual address. The first paging table entry stores a second base address of a second paging table. The translation unit may also be configured to access a second paging table entry using the second base address and a second offset comprised within a second portion of the virtual address. The second paging table entry stores a third base address of a third paging table. The translation unit may be configured to access a third paging table entry using the third base address and a third offset comprised within a third portion of the virtual address, and the third paging table entry may store a fourth base address of a fourth paging table. Similarly, the translation unit may be configured to access a fourth paging table entry using the third base address and a third offset comprised within a third portion of the virtual address, and the fourth paging table entry may store a base address of a page of physical memory. The translation unit may then be configured to obtain the physical address by concatenating the base address of the page of physical memory with a final offset comprised within a final portion of the virtual address. In some embodiments, a processor configured to translate virtual addresses may be included within a computer system.
In another embodiment, a method of translating a virtual address into a physical address is disclosed. The method includes locating a first entry within a first paging table using a first pointer to the first paging table and a first offset comprised within a first portion of the virtual address. The first entry within the first paging table stores a second pointer to a second paging table. A second entry in the second paging table may be located using the second pointer and a second offset comprised within a second portion of the virtual address. The second entry stores a third pointer to a third paging table, and thus a third entry in the third paging table may be located using the third pointer and a third offset included in a third portion of the virtual address. The third entry stores a fourth pointer to a fourth paging table, allowing a fourth entry in the fourth paging table to be located using the fourth pointer and a fourth offset comprised within a fourth portion of the virtual address. The fourth entry may store a final pointer to (base address of) a page of physical memory. The physical address may be obtained by concatenating the base address of the page of physical memory with a final offset comprised within a final portion of the virtual address.
In another embodiment, a plurality of paging system data structures are stored on a carrier medium. The paging system data structures may comprise a first paging table comprising a plurality of first paging table entries, one or more second paging tables, wherein each second paging table comprises a plurality of second paging table entries, one or more third paging tables, wherein each third paging table comprises a plurality of third paging table entries, and one or more fourth paging tables, wherein each fourth paging table comprises a plurality of fourth paging table entries. Each fourth paging table entry may be configured to store a base address of a physical page in memory. Each first paging table entry may be configured to store a base address of one of the second paging tables. Similarly, each second paging table entry may be configured to store a base address of one of the third paging tables, and each third paging table entry may be configured to store a base address of one of the fourth paging tables. In one embodiment, the paging system data structures may include six paging tables.
In other embodiments, multiple program instructions may be stored on a carrier medium. The program instructions are computer-executable to locate a first entry within a first paging table using a first pointer to the first paging table and a first offset comprised within a first portion of the virtual address, wherein the first entry within the first paging table comprises a second pointer to a second paging table. The program instructions are similarly computer-executable to locate a second entry within the second paging table using the second pointer to the second paging table and a second offset comprised within a second portion of the virtual address. The second entry comprises a third pointer to a third paging table. The program instructions are computer-executable to locate a third entry within the third paging table using the third pointer to the third paging table and a third offset comprised within a third portion of the virtual address, wherein the third entry comprises a fourth pointer to a fourth paging table. Also, the program instructions are computer-executable to locate a fourth entry within the fourth paging table using the fourth pointer to the fourth paging table and a fourth offset comprised within a fourth portion of the virtual address, wherein the fourth entry comprises a final pointer to (base address of) a page of physical memory. The program instructions are also computer-executable to obtain the physical address by concatenating the a base address of the page of physical memory with a final offset comprised within a final portion of the virtual address.
In another embodiment, a processor may include an execution core configured to generate a virtual address and a translation unit configured to translate the virtual address to a physical address. The translation unit may be configured to perform the address translation using either of two possible page mapping mechanisms that support virtual addresses having up to a first number of bits (e.g., 32 bits) and another page mapping mechanism that supports virtual addresses having more than that number of bits. The page mapping mechanism used may depend on the operating mode of the processor.
A processor may be configured to translate a virtual address to a physical address using several different sets of paging tables in another embodiment. In one set of paging tables, each paging table entry may have a first size (e.g., 4 bytes). In two other sets of paging tables, each paging table entry may have a second size (e.g., 8 bytes). The second two sets of paging tables (having second-sized entries) may each include different numbers of levels of paging tables. The set of paging tables with more levels of paging tables may support virtual addresses having more bits than the other set of paging tables supports.
In still another embodiment, a processor may be configured to translate virtual addresses to physical addresses using different sets of paging tables depending on which operating mode the processor is in. The same range of virtual address bits may be used to index a table in each of two different sets of tables. For example, the range of virtual address bits 20:12 may be used to index a table in both a first and a second set of paging tables.